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The StrongARM SA-110 is a CPU designed by Digital and manufactured by Digital and Intel. It was sampled in 1995 and released in 1996.


The SA-110 implements the ARMv4 instruction set. The integer pipeline is 5 stages, allowing for the majority of instructions to execute in a single cycle.

The SA-110 uses a Harvard architecture cache, with 16kB for instructions and 16kB for data. The data cache implements a write-back policy. Caches use 32-byte lines. The write buffer contains 4 entries of 4 words each, and implements write combining.

The SA-110 has no coprocessor bus and can not be connected to an FPA.

Use in the RiscPC

When used in the RiscPC, the SA-110 must use the "standard" bus mode. In this mode, cache line fill wrapping is disabled (this would have fetched the critical or addressed word first, reducing latency), and much of the write combining functionality is disabled. The StrongARM CPU card also appears to limit read/write bursts to 4 words.

The instruction and data caches do not implement any form of coherency. This means that self modifying code and other similar techniques do not work. RISC OS 3.7 was modified to avoid this issue, but most third party software required patching to run on a StrongARM.

SA-110 will not perform burst reads or writes into uncached memory. This causes reduced VRAM bandwidth, limiting performance of graphical applications such as games. A third party module AutoVCache was written to remap VRAM as cached memory, flushing the cache as required. This functionality was later built into RISC OS 4.

The SA-110 prior to revision T has a bug in the LDMIB instruction that prevents demand paging from functioning correctly. This affected the "lazy task swapping" feature of RISC OS 4, which is disabled on affected chips.


The SA-110 was used in the following computers :

  • RiscPC (ART10/200MHz and ART12/233MHz processor cards)
  • Omega