From Arc Wiki

This teeny-tiny article needs some work. You can help us by expanding it.

The ARM810 is a CPU designed by ARM Ltd for Acorn Computers Ltd, which sampled in 1996. It never made it to production.


The ARM810 integrates an ARM8 core, MMU, 8kB cache and 8 entry write buffer. The CPU core supports 26 and 32 bit modes, and implements the ARMv4 instruction set.

In a departure from previous ARM CPU cores, the ARM8 implements a 5-stage integer pipeline. The longer pipeline allows for memory instructions to execute in a single cycle, and allows higher clock speeds. The CPU includes a dedicated prefetch unit, which implements static branch prediction. ARM claimed that the ARM8 CPU core had 35% lower CPI (Cycles Per Instruction) than ARM7.

The cache is unified, but is now write-back and allows reading of two words per cycle. This allows LDM instructions to execute at two loads per cycle.


ARM8 CPUs (in the form of "ARM800") were advertised as a "future upgrade" at the RiscPC launch in 1994. Sample ARM810 chips were delivered to Acorn Computers Ltd and evaluated in early 1996. It was decided that the 202 MHz StrongARM was a superior option to the 72 MHz ARM810 so the latter was never released.